Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates - Exclusive Portal for VLSI Jobs

Search Jobs

	0 Functional Areas selected select all \| select none \| close
Location :	Experience :	Search

Featured Technologies

Featured Jobs

View

Refer

Apply

Standard Cell Layout

Job description Role :Standard Cell layout Engineer Job Location :Bangalore Qualification :BE/ME/B.Tech/M.TechDiploma Experience :2 – 6 Years

Updated: 2013-May-25 01:07 AM

Industry: SemiconductorRole: Standard cell Layout Engineer

Experience Level: 2.0 to 6.0 yrsLocation: Bangalore (India)

Employer: Standard cell layout

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

View

Refer

Apply

Standard Cell Layout

Job description Role :Standard Cell layout Engineer Job Location :Bangalore Qualification :BE/ME/B.Tech/M.TechDiploma Experience :2 – 6 Years

Updated: 2013-May-25 01:07 AM

Industry: SemiconductorRole: Standard cell Layout Engineer

Experience Level: 2.0 to 6.0 yrsLocation: Bangalore (India)

Employer: Standard cell layout

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

View

Refer

Apply

ASIC Verification Engineer Jobs at USA

ASIC Verification Engineer Good hands on exp in System verilog Exposure to any of the methodology Knowledge on any p rotocols

Updated: 2013-May-23 10:06 AM

Industry: SemiconductorRole: Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: California (United States)

Employer: Design Verification

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

View

Refer

Apply

Verification engineers for Bangalore

ASIC Verification Engineer Good hands on exp in System verilog Exposure to any of the methodology Knowledge on any p rotocols

Updated: 2013-May-22 07:01 PM

Industry: SemiconductorRole: Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: Bangalore (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

View

Refer

Apply

Analog layout engineers for Malaysia

Analog Layout Engineer Good Knowledge about Analog Layout, should have work experience on 45nm (Below 45nm is highly preferable) Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS. Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation...

Updated: 2013-May-22 06:58 PM

Industry: SemiconductorRole: Layout Engineer

Experience Level: 3.0 to 7.0 yrsLocation: Bangalore (India)

Employer: Analog Layout

Keywords: "analog layout"

View

Refer

Apply

Onsite opportunity for Physical design engineers

Physical design engineers Expertise in Physical design tools Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing. Sound expertise in Tcl, Perl, Shell scripting

Updated: 2013-May-22 06:40 PM

Industry: SemiconductorRole: Physical Design

Experience Level: 3.0 to 8.0 yrsLocation: Bangalore (India)

Employer: Physical Design

Keywords: Physical Design Soc Encounter ICC Synopsys ICC Soc Encounter ICC Synopsys ICC Soc Encounter ICC Synopsys ICC

View

Refer

Apply

ASIC Verification Engineers at Chennai

ASIC Verification Engineer Good hands on exp in System verilog Exposure to any of the methodology Knowledge on any p rotocols

Updated: 2013-May-22 06:27 PM

Industry: SemiconductorRole: Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: Chennai (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

View

Refer

Apply

Circuit Design Experts - Salary 25 to 40 Lakhs+

Circuit Design Experts 1. Memory Circuit Design Engineers 2. I/O Circuit Design Engineers 3. Standard Cell Library Development

Updated: 2013-May-22 06:14 PM

Industry: SemiconductorRole: Circuit Design

Experience Level: 6.0 to 11.0 yrsLocation: Bangalore (India)

Employer: Circuit Design Engineer

Keywords: VLSI Circuit Design Memory Design I / O Design Library Development Memory Design I / O Design Library Development Memory Design I / O Design Library Development

View

Refer

Apply

System Verilog Experts

Job description Role: ASIC Verification Engineer Years of Experience:3 -10 Years Qualification: BE/ME/BTECH/MTECH Job Location: Bangalore Email your updated CV to saku@vlsijobs.net

Updated: 2013-May-19 01:04 AM

Industry: Semiconductor, HardwareRole: Verification Engineer

Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM OVM VMM OVM VMM

View

Refer

Apply

R&D Engineer jobs (C/C++)with a EDA Company @ Bangalore

R D Engineer (C/C++ with Data Structure Algorithm) jobs opportunity with a EDA Company @ Bangalore Job Description:- • BTech/MTech in Electronics Communication - Excellent academic background. • 0.6 to 3 years of C/C++/Perl development in EDA domain. • Sound understanding with algorithm, DS...

Updated: 2013-May-19 01:04 AM

Industry: SemiconductorRole: R&D Engineer

Experience Level: 0.6 to 3.0 yrsLocation: Bangalore (India)

Employer: EDA Tool Developer

Keywords: C C++ EDA algorithm algorithm algorithm

browse all jobs

Business Meeting with one of our VLSI client

We use TooStep Id for authentication. What is it?

Post Your Resume Now !

Create a confidential Career Profile and Resume/C.V. online
Get advice for planning their career and for marketing of experience and skills
Maximize awareness of and access to the best career opportunities

Login with LinkedIn Or, sign up via facebook or twitter
Already have an account?
Email Id:
Password:
Forgot password?		Remember me
		Log In or Sign Up

Full name*:
Email address*:
New password*:
	Sign Up
By clicking 'Sign up' above you are agreeing to the Terms of Service and Privacy Policy of TooStep