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System Verilog / Physical Design / RTL Design - Salary 40 - 50 Lakhs

Experience : 4 - 10 Years Location : Bangalore Candidate should have hands on experience on any of the two following skill sets 1.Expertise in ASIC / SOC Verification using System Verilog. 2.Hands on experience in OVM , VMM, UVM methodology. 3.Experience using Synopsys ICC, Magma Talus, Cadence...

Updated: 2013-Jun-18 01:14 AM

Industry: SemiconductorRole: ASIC Design Engineers

Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)

Employer: Semiconductor Jobs

Keywords: ASIC Verilog RTL System Verilog Physical Design Synthesis System Verilog Physical Design Synthesis System Verilog Physical Design Synthesis

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RTL Design Jobs Greater Noida

RTL Design with exposure of DSP, MATLAB/SIMULINK, Verilog/VHDL, Synopsys Design Compiler. If you are interested please mail your updated CV to seemant@roljobs.com along with your Current CTC: Expected CTC: Notice Period Required:

Updated: 2013-Jun-09 01:04 AM

Industry: SemiconductorRole: RTL Design

Experience Level: 3.0 to 10.0 yrsLocation: Noida (India)

Employer: RTL Design Engineer

Keywords: DSP MATLAB/SIMULINK RTL Design Verilog/VHDL

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ASIC Verification Engineer jobs @ Chennai

Job Description: - Role: ASIC Verification Engineer Years of Experience: 3 to 8 Years Job Location: Chennai QUALIFICATIONS: BE/B.Tech/ME/M.Tech Professionals interested in exploring this opportunity, Can revert with your updated resume on saku@roljobs.com

Updated: 2013-Jun-09 01:04 AM

Industry: SemiconductorRole: ASIC Verification Engineer

Experience Level: 3.0 to 8.0 yrsLocation: Chennai (India)

Employer: Design Verification

Keywords: System Verilog PCIE DDR USB PCIE DDR USB PCIE DDR USB

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R&D Engineer jobs (C/C++)with a EDA Company @ Bangalore

R D Engineer (C/C++ with Data Structure Algorithm) jobs opportunity with a EDA Company @ Bangalore Job Description:- • BTech/MTech in Electronics Communication - Excellent academic background. • 0.6 to 3 years of C/C++/Perl development in EDA domain. • Sound understanding with algorithm, DS...

Updated: 2013-Jun-09 01:04 AM

Industry: SemiconductorRole: R&D Engineer

Experience Level: 0.6 to 3.0 yrsLocation: Bangalore (India)

Employer: EDA Tool Developer

Keywords: C C++ EDA algorithm algorithm algorithm

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Circuit Design Experts - Salary 25 to 40 Lakhs+

Circuit Design Experts 1. Memory Circuit Design Engineers 2. I/O Circuit Design Engineers 3. Standard Cell Library Development

Updated: 2013-Jun-09 01:04 AM

Industry: SemiconductorRole: Circuit Design

Experience Level: 6.0 to 11.0 yrsLocation: Bangalore (India)

Employer: Circuit Design Engineer

Keywords: VLSI Circuit Design Memory Design I / O Design Library Development Memory Design I / O Design Library Development Memory Design I / O Design Library Development

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Standard Cell Layout

Job description Role :Standard Cell layout Engineer Job Location :Bangalore Qualification :BE/ME/B.Tech/M.TechDiploma Experience :2 – 6 Years

Updated: 2013-Jun-08 01:04 AM

Industry: SemiconductorRole: Standard cell Layout Engineer

Experience Level: 2.0 to 6.0 yrsLocation: Bangalore (India)

Employer: Standard cell layout

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

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System Verilog Engineer jobs @ USA (H1 is Must)

Job Description: - Role: ASIC Verification Engineer Years of Experience: 4 to 8 Years Job Location: Chennai QUALIFICATIONS: BE/B.Tech/ME/M.Tech Professionals interested in exploring this opportunity, Can revert with your updated resume on saku@roljobs.com

Updated: 2013-Jun-04 11:51 PM

Industry: SemiconductorRole: ASIC Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: USA (United States)

Employer: Design Verification

Keywords: System Verilog PCIE DDR USB PCIE DDR USB PCIE DDR USB

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System Verilog Engineer jobs @ Chennai

Job description Role: ASIC Verification Engineer Years of Experience:4 -9 Years Qualification: BE/ME/BTECH/MTECH Job Location: Chennai Email your updated CV to saku@vlsijobs.net

Updated: 2013-Jun-04 11:44 PM

Industry: Semiconductor, HardwareRole: Verification Engineer

Experience Level: 4.0 to 9.0 yrsLocation: Chennai (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM OVM VMM OVM VMM

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Standard Cell library development jobs with a Product based MNC @ Bangalore

Job description Role :Standard Cell library Engineer Job Location :Bangalore Qualification :BE/ME/B.Tech/M.TechDiploma Experience :3 – 7 Years

Updated: 2013-Jun-04 11:42 PM

Industry: SemiconductorRole: Standard cell Layout Engineer

Experience Level: 3.0 to 7.0 yrsLocation: Bangalore (India)

Employer: Standard cell layout

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

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Standard Cell Layout

Job description Role :Standard Cell layout Engineer Job Location :Bangalore Qualification :BE/ME/B.Tech/M.TechDiploma Experience :2 – 6 Years

Updated: 2013-May-25 01:07 AM

Industry: SemiconductorRole: Standard cell Layout Engineer

Experience Level: 2.0 to 6.0 yrsLocation: Bangalore (India)

Employer: Standard cell layout

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

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ASIC Verification Engineer Jobs at USA

ASIC Verification Engineer Good hands on exp in System verilog Exposure to any of the methodology Knowledge on any p rotocols

Updated: 2013-May-23 10:06 AM

Industry: SemiconductorRole: Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: California (United States)

Employer: Design Verification

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

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Verification engineers for Bangalore

ASIC Verification Engineer Good hands on exp in System verilog Exposure to any of the methodology Knowledge on any p rotocols

Updated: 2013-May-22 07:01 PM

Industry: SemiconductorRole: Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: Bangalore (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

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Analog layout engineers for Malaysia

Analog Layout Engineer Good Knowledge about Analog Layout, should have work experience on 45nm (Below 45nm is highly preferable) Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS. Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation...

Updated: 2013-May-22 06:58 PM

Industry: SemiconductorRole: Layout Engineer

Experience Level: 3.0 to 7.0 yrsLocation: Bangalore (India)

Employer: Analog Layout

Keywords: "analog layout"

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Onsite opportunity for Physical design engineers

Physical design engineers Expertise in Physical design tools Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing. Sound expertise in Tcl, Perl, Shell scripting

Updated: 2013-May-22 06:40 PM

Industry: SemiconductorRole: Physical Design

Experience Level: 3.0 to 8.0 yrsLocation: Bangalore (India)

Employer: Physical Design

Keywords: Physical Design Soc Encounter ICC Synopsys ICC Soc Encounter ICC Synopsys ICC Soc Encounter ICC Synopsys ICC

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ASIC Verification Engineers at Chennai

ASIC Verification Engineer Good hands on exp in System verilog Exposure to any of the methodology Knowledge on any p rotocols

Updated: 2013-May-22 06:27 PM

Industry: SemiconductorRole: Verification Engineer

Experience Level: 4.0 to 8.0 yrsLocation: Chennai (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

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System Verilog Experts

Job description Role: ASIC Verification Engineer Years of Experience:3 -10 Years Qualification: BE/ME/BTECH/MTECH Job Location: Bangalore Email your updated CV to saku@vlsijobs.net

Updated: 2013-May-19 01:04 AM

Industry: Semiconductor, HardwareRole: Verification Engineer

Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)

Employer: Design Verification

Keywords: System Verilog OVM VMM OVM VMM OVM VMM

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Onsite Opportunity for Analog Layout Experts

Experience : 3 - 8 Years Location : Malaysia Layout Design of Analog circuits such as Op-Amps, Regulators, ADC, DAC. Expertise in EDA tools for Layout Design :Virtuoso, L-Edit, Assura , Calibre Layout Design of IO Cells / AMS etc Exposure to latest Technology (45nm , 32nm, 22nm)...

Updated: 2013-May-11 01:06 AM

Industry: SemiconductorRole: Layout Design

Experience Level: 3.0 to 8.0 yrsLocation: Bangalore (India)

Employer: Analog Layout

Keywords: Analog Layout Mixed Signal Layout Virtuoso IO Cells Library Development IO Cells Library Development IO Cells Library Development

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Analog/Mixed signal Layout Engineer jobs @ Bangalore

Position : Analog Layout Engineer, Experience : 4 - 7 Years, Job Location : Bangalore, Education:Diploma/BE/B.Tech/ME/M.Tech/MS/MSC/MCA Email your updated CV to saku@vlsijobs.net

Updated: 2013-May-11 01:06 AM

Industry: SemiconductorRole: Layout Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Employer: Analog Layout

Keywords: "analog layout" "Mixed signal layout" "IO layout" "IO Pad" "IO Ring" "IO Block" "IO Cells"

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Memory / IO Cricuit Design Specialists - Salary 30 - 40 Lakhs+

Experience : 7 - 13 Years Job Location : Bangalore PhD / Masters in Electrical or Electronics Engineering. Experience in development of analog, mixed signal circuits and layouts of Memories (SRAM / ROM) / IO. Expertise in Circuit Design Techniques. Good understanding of Semiconductor...

Updated: 2013-May-03 03:44 PM

Industry: SemiconductorRole: Memory Design

Experience Level: 7.0 to 13.0 yrsLocation: Bangalore (India)

Employer: Circuit Design Engineer

Keywords: Memory Design IO Design VLSI Circuit Design Clock gating SRAM CMOS Clock gating SRAM CMOS Clock gating SRAM CMOS

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Physical Design Engineer jobs @ Noida

Job Description : 3 to 10 Year of experience in doing hands on physical design Preferred Magma Talus experience or Synopsys ICC on at least two project. St rong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure,...

Updated: 2013-Apr-30 10:59 AM

Industry: SemiconductorRole: Physical Design

Experience Level: 3.0 to 10.0 yrsLocation: Noida (India)

Employer: Physical Design

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Recent Jobs

Keywords: ASIC Verilog RTL System Verilog Physical Design Synthesis System Verilog Physical Design Synthesis System Verilog Physical Design Synthesis

Keywords: DSP MATLAB/SIMULINK RTL Design Verilog/VHDL

Keywords: System Verilog PCIE DDR USB PCIE DDR USB PCIE DDR USB

Keywords: C C++ EDA algorithm algorithm algorithm

Keywords: VLSI Circuit Design Memory Design I / O Design Library Development Memory Design I / O Design Library Development Memory Design I / O Design Library Development

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

Keywords: System Verilog PCIE DDR USB PCIE DDR USB PCIE DDR USB

Keywords: System Verilog OVM VMM OVM VMM OVM VMM

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

Keywords: "Standard cell Layout"/Standard Cell/Std Cell

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

Keywords: "analog layout"

Keywords: Physical Design Soc Encounter ICC Synopsys ICC Soc Encounter ICC Synopsys ICC Soc Encounter ICC Synopsys ICC

Keywords: System Verilog OVM VMM UVM OVM VMM UVM OVM VMM UVM

Keywords: System Verilog OVM VMM OVM VMM OVM VMM

Keywords: Analog Layout Mixed Signal Layout Virtuoso IO Cells Library Development IO Cells Library Development IO Cells Library Development

Keywords: "analog layout" "Mixed signal layout" "IO layout" "IO Pad" "IO Ring" "IO Block" "IO Cells"

Keywords: Memory Design IO Design VLSI Circuit Design Clock gating SRAM CMOS Clock gating SRAM CMOS Clock gating SRAM CMOS

Keywords: Physical Design First encounter Soc Encounter ICC Synopsys ICC