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Micro Architect Experts

Strong micro-architecture and logic designing skills. Working exposure to chip level functional verification Good Knowledge of Verilog HDL language and RTL coding techniques with DFT techniques is a must. Experience with Processor is a must. Strong technical background in IC / SOC design and...

Updated: 2012-Aug-11 05:30 AM

Industry: SemiconductorRole: Logic Design

Experience Level: 3.0 to 15.0 yrsLocation: Noida (India)

Employer: RTL Design Engineer

Keywords: ASIC Design RTL Micro Architecture VHDL Verilog VHDL Verilog VHDL Verilog

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Micro Architect Experts @ Hyderabad

Job Details : ASIC/FPGA Design(Digital) Detailed Description of the Job Profile: This person will be leading a team of senior engineers. He will be involved in recruiting, training these engineers. He will be responsible for visiting customer site, understanding customer requirements as lead...

Updated: 2012-Jul-27 06:58 PM

Industry: SemiconductorRole: Logic Design Engineer

Experience Level: 3.0 to 15.0 yrsLocation: Bangalore Hyderabad Noida (India)

Employer: ASIC FPGA Engineers

Keywords: RTL

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Front End Design Jobs

Micro-architecture and RTL. DFT ATPG. STA and Timing closure.

Updated: 2012-Aug-18 12:30 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Greater Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs

Micro-architecture and RTL. DFT ATPG. STA and Timing closure.

Updated: 2012-Aug-17 05:00 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Greater Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs

Micro-architecture and RTL. DFT ATPG. STA and Timing closure.

Updated: 2012-Aug-11 12:18 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Greater Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs

Micro-architecture and RTL. DFT ATPG. STA and Timing closure.

Updated: 2012-Aug-10 04:21 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Greater Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Sep-22 06:06 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC DFT Synthesis

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-25 01:15 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC DFT Synthesis

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-17 05:08 PM

Industry: SemiconductorRole: Front End Design Jobs

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs at Noida

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-11 01:19 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC DFT Synthesis

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-11 12:57 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Jobs for Frontend designing with Product Based MNC at Greater Noida

Must have experience on frontend The incumbent will be responsible for the Front-end digital ASIC design activities of ARM CPUs based sub-systems: The job involves: a. Micro-architecture and RTL

Updated: 2012-Aug-10 06:02 PM

Industry: SemiconductorRole: Frontend Designer

Experience Level: 5.0 to 8.0 yrsLocation: Greater Noida (India)

Employer: Semiconductor Jobs

Keywords: Frontend RTL Verilog

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-08 06:24 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-08 05:40 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Jobs for Frontend designing with Product Based MNC at Greater Noida

Must have experience on frontend The incumbent will be responsible for the Front-end digital ASIC design activities of ARM CPUs based sub-systems: The job involves: a. Micro-architecture and RTL

Updated: 2012-Aug-08 05:23 PM

Industry: SemiconductorRole: Frontend Designer

Experience Level: 5.0 to 8.0 yrsLocation: Greater Noida (India)

Employer: Semiconductor Jobs

Keywords: Frontend RTL Verilog

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Aug-08 05:20 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT

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Front End Design Jobs in Greater Noida

Responsibilities : - Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Jul-21 11:37 AM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Greater Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT Verilog Front End VLSI Verilog Front End VLSI Verilog Front End VLSI

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Front End Design Jobs at Noida

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Jul-21 11:07 AM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT Front End Front End Front End

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Front End Design (VLSI) Jobs in Delhi/NCR

Responsibilities : - Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Jul-20 09:45 AM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: New Delhi NCR (India)

Employer: ASIC DESIGN

Keywords: ASIC Synthesis DFT Verilog Front End VLSI Verilog Front End VLSI Verilog Front End VLSI

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Front End Design Jobs

Micro-architecture and RTL. - Synthesis and equivalence checks (low power Flow). - DFT ATPG. - STA and Timing closure. - Interaction with the RTL / PD team to achieve area, timing and power goals.

Updated: 2012-Jul-18 05:45 PM

Industry: SemiconductorRole: Sr Embedded Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Noida (India)

Employer: ASIC DESIGN

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